1. Field of the Invention
The present invention relates to a memory circuit, a method of access, and a method of preparation of data in the design of a circuit using a read only memory (ROM) or other memory Which enable a memory with redundancy of data (hereinafter referred to as a "redundancy-ridden memory" or "redundant memory") to be transformed to a memory without redundancy of data (hereinafter referred to as a "redundancy-free memory") and the size of the circuit to thereby be reduced.
2. Description of the Related Art
One example of a circuit using a read only memory is a discrete cosine transformation (DCT) circuit. An explanation will first be made of this.
Discrete cosine transformation is a method of transformation used in the field of image compression etc. More specifically, 8th order discrete cosine transformation involves calculation of the following equations:
______________________________________ F0 = C4 .times. D0 + C4 .times. D1 + C4 .times. D2 + C4 .times. D3 + C4 .times. D4 + C4 .times. D5 + C4 .times. D6 + C4 .times. D7 F1 = C1 .times. D0 + C3 .times. D1 + C5 .times. D2 + C7 .times. D3 - C7 .times. D4 - C5 .times. D5 - C3 .times. D6 - C1 .times. D7 F2 = C2 .times. D0 + C6 .times. D1 - C6 .times. D2 - C2 .times. D3 - C2 .times. D4 - C6 .times. D5 + C6 .times. D6 + C2 .times. D7 F3 = C3 .times. D0 - C7 .times. D1 - C1 .times. D2 - C5 .times. D3 + C5 .times. D4 + C1 .times. D5 + C7 .times. D6 - C3 .times. D7 F4 = C4 .times. D0 - C4 .times. D1 - C4 .times. D2 + C4 .times. D3 + C4 .times. D4 - C4 .times. D5 - C4 .times. D6 + C4 .times. D7 F5 = C5 .times. D0 - C1 .times. D1 + C7 .times. D2 + C3 .times. D3 - C3 .times. D4 - C7 .times. D5 + C1 .times. D6 - C5 .times. D7 F6 = C6 .times. D0 - C2 .times. D1 + C2 .times. D2 - C6 .times. D3 - C6 .times. D4 + C2 .times. D5 - C2 .times. D6 + C6 .times. D7 F7 = C7 .times. D0 - C5 .times. D1 + C3 .times. D2 - C1 .times. D3 + C1 .times. D4 - C3 .times. D5 + C5 .times. D6 - C7 .times. ______________________________________ D7
Here, D0 to D7 show input data and F0 to F7 show output data. Further, C1 to C7 are constants (coefficient data) and Ci=cos (i.times..pi./16).
FIG. 1 shows an example of the configuration of an inner product calculation circuit which receives as input the data D0 to D7 and calculates and outputs the data F2. In FIG. 1, reference numeral 1 represents a control circuit (CTL), 2 represents a read only memory (ROM), 3 represents a multiplication and addition (product-sum) calculator, WA0, WA1, and WA2 represent address signal lines, WD represents an input signal line, WCOE represents a coefficient signal line, and WF represents an output signal line. Note that in FIG. 1, WD, WCOE, and WF represent bus lines, while WA0, WA1, and WA2 represent one-bit lines.
In this circuit, the data D0 to D7 applied to from the input terminal IN are input through the input signal line WD to the multiplication and addition calculator 3.
Further, addresses (4.times.WA2+2.times.WA1+WA0) are applied to the read only memory 2 from the control circuit 1 through the address signal lines WA0, WA1, and WA2.
The read only memory 2 is for example an eight-word read only memory. As shown in FIG. 3, the coefficient data Ci and -Ci (where, i=2, 6) are stored at the 0-th to 7-th addresses.
The data stored corresponding to the addresses given from the control circuit 1 are output from the read only memory 2 to the coefficient signal line WCOE. The coefficient data output to the coefficient signal line WCOE are input to the multiplication and addition calculator 3.
In the multiplication and addition calculator 3, the inner product between the input data and the coefficient data are calculated. The result of the calculation, that is, the data F2, is output through the output signal line WF to the output terminal OUT.
FIGS. 2A to 2D are timing charts of the circuit of FIG. 1. The operation of the circuit of FIG. 1 will be explained in more detail based on these timing charts.
The data D0, D1, D2, . . . , D7 are successively input from the input terminal IN as shown in FIG. 2A.
The address signals (4.times.WA2+2.times.WA1+WA0) from the control circuit 1 are, as shown in FIG. 2B, "0", "1", "2", . . . , "7". Due to these address signals, the read only memory 2 outputs, as shown in FIG. 2C, the coefficient data "C2", "C6", "-C2", "-C2", "-C6", "C6", and "C2".
In the multiplication and addition calculator 3, the data D0 (FIG. 2A) and the coefficient C2 (FIG. 2C) are multiplied at the first cycle, the data D1 (FIG. 2A) and the coefficient C6 (FIG. 2C) are multiplied at the second cycle, and the data of FIG. 2A and the data of FIG. 2C are multiplied in the following third to eighth cycles as well.
In the multiplication and addition calculator 3, further, the results of the first to eighth cycle multiplication operations are cumulatively added as well.
At the end of the eighth cycle, in the multiplication and addition calculator 3, F2=C2.times.D0+C6.times.D1-C6.times.D2-C2.times.D3-C2.times.D4-C6.times.D5 +C6.times.D6+C2.times.D7 is calculated and the data F2 is output from the output terminal OUT as shown in FIG. 2D.
As will be understood from the above explanation, the control circuit 1 of FIG. 1 is comprised of a counter which counts from "0" to "7".
Further, the data to be stored at the i (i=0 to 7)-th address of the read only memory 2 of FIG. 3 is the value of data to be multiplied with the input data Di. Accordingly, it is simple to design a circuit of FIG. 1 (data of ROM Shown in FIG. 3) as the circuit for calculating the value F2.
However, such an easy-to-design circuit has redundancy of data and therefore ends up large in size. That is, the read only memory of FIG. 1 is a redundancy-ridden read only memory.
In the past, there has never been a method of transforming such an easy-to-design redundancy-ridden read only memory (for example, the ROM of FIG. 1) to a redundancy-free read only memory, so hardware had to be made based on a circuit designed with redundancy and it was only possible to fabricate a circuit large in size.
The flow of the design process is shown in FIG. 4. A step a of FIG. 4, a circuit including a redundancy-ridden memory circuit is designed. As shown in step b of FIG. 4, hardware is then made based on the circuit including the redundancy-ridden memory circuit as designed.
The hardware actually constructed by the conventional design process shown in FIG. 4 therefore suffered from the disadvantage of a large circuit size.